My PhD advisors are Éric Violard, Michel Mehrenberger and Sever Hirstoaga.

My thesis is entitled “Pic-Vert: A Particle-in-Cell Implementation for Multi-Core Architectures”.

Abstract (1 000 words)

In this thesis, we are interested in solving the Vlasov–Poisson system of equations (useful in the domain of plasma physics, for example within the ITER project), thanks to classical Particle-in-Cell (PIC) and semi-Lagrangian methods.
The main contribution of our thesis is an efficient implementation of the PIC method on multi-core architectures, written in C, called Pic-Vert. Our implementation
(a) achieves close-to-minimal number of memory transfers with the main memory,
(b) exploits SIMD instructions for numerical computations, and
(c) exhibits a high degree of shared memory parallelism.
To put our work in perspective with respect to the state-of-the-art, we propose a metric to compare the efficiency of different PIC implementations when using different multi-core architectures. Our implementation is 3 times faster than other recent implementations on the same architecture (Intel Haswell).

Manuscript (232 pages, approximatively 15 MB)

The manuscript is available at the following link.

Slideshow (36 slides, approximatively 3 MB)

This thesis was defended with the following slides (click on the references or on the names of other implementations to get the corresponding papers).

Source and Script Files (175 files, approximatively 600 kB)

Our implementation earned a “Best Artifact Award” at Euro-Par 2018, at the following link. This link includes source files, documentation together with compile, run and post-process scripts.

A more complete list of the source files of Pic-Vert is available at the following link (still working to make this repository easy to use).

Comparison to Other Implementations (in 3d)

Comparison to different implementations on different architectures: cores, memory bandwidth in GB/s, number of particles processed by second (absolute and normalized w.r.t. memory bandwidth — higher is better). All the implementations use linear interpolation (except PIConGPU which uses second order interpolation). Click on the names of other implementations to get the corresponding papers.

Top: CPUs. Bottom: accelerators (GPUs, MICs).

Implementation Architecture Nb. cores Memory bandwidth (GB/s) Nb. particles / s Normalized
VPIC (2008) IBM PowerXCell 8i 0009 204.8 0173 · 10^6 00.85
OSIRIS (2013) Intel Xeon E5-2680 0008 051.2 0134 · 10^6 02.62
ORB5 (2016) Intel Xeon E5-2670 0008 051.2 0069 · 10^6 01.35
PICADOR (2016) Intel Xeon E5-2697 v3 0014 068 0127 · 10^6 01.87
GTC-P (2016) Intel Xeon E5 2692 v2 0012 059.7 0100 · 10^6 01.68
PIConGPU (2016) Intel Xeon E5-2698 v3 0016 068 0111 · 10^6 01.63
Pic-Vert (2018) Intel Xeon Platinum 8160 0024 128 0740 · 10^6 05.78
Pic-Vert (2018) Intel Xeon E5-2690 v3 0012 068 0374 · 10^6 05.49
PIConGPU (2016) NVIDIA Tesla GK210 2496 480 0336 · 10^6 00.70
ORB5 (2016) NVIDIA Tesla K20X 2688 250 0177 · 10^6 00.71
PICADOR (2016) Intel Xeon Phi 7250 (KNL) 0068 115.2 0298 · 10^6 02.59
EMSES (2017) Intel Xeon Phi 7250 (KNL) 0068 115.2 1300 · 10^6 11.3


Back to my homepage.